Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A linear-time transformation of linear inequalities into conjunctive normal form
Information Processing Letters
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Threshold logic circuit design of parallel adders using resonant tunneling devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Generic ILP versus specialized 0-1 ILP: an update
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Threshold Logic Synthesis Tool for RTD Circuits
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Combinational equivalence checking for threshold logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Increased Logic Functionality of Clocked Series-Connected RTDS
IEEE Transactions on Nanotechnology
On rewiring and simplification for canonicity in threshold logic circuits
Proceedings of the International Conference on Computer-Aided Design
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metal-oxide semiconductor (CMOS) technology in future circuit design. However, many nanotechnologies are intrinsically suitable for implementing threshold logic rather than Boolean logic which has dominated CMOS technology in the past. To fully take advantage of such emerging nanotechnologies, efficient design automation tools for threshold logic therefore become essential. In this work, we propose novel techniques of formulating a given threshold logic in conjunctive normal form (CNF) that facilitates efficient SAT-based equivalence checking. Three different strategies of CNF generation from threshold logic representations are implemented. Experimental results based on MCNC benchmarks are presented as a complete comparison. Our hybrid algorithm, which takes into account input symmetry as well as input weight order of threshold gates, can efficiently generate CNF formulas in terms of both SAT solving time and CNF generating time.