Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On applying incremental satisfiability to delay fault testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A machine program for theorem-proving
Communications of the ACM
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Solving satisfiability in combinational circuits with backtrack search and recursive learning
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Checking equivalence for partial implementations
Proceedings of the 38th annual Design Automation Conference
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Combinational equivalence checking through function transformation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Local Search for Boolean Relations on the Basis of Unit Propagation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An effective and efficient ATPG-based combinational equivalence checker
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Logic verification based on diagnosis techniques
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
BerkMin: A fast and robust Sat-solver
Discrete Applied Mathematics
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Merging nodes under sequential observability
Proceedings of the 45th annual Design Automation Conference
Bit-precise reasoning with affine functions
SMT '08/BPR '08 Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel formal verification approach for RTL hardware IP cores
Computer Standards & Interfaces
Scalable formula decomposition for propositional satisfiability
Proceedings of the Third C* Conference on Computer Science and Software Engineering
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability
Proceedings of the Conference on Design, Automation and Test in Europe
Simulation-based equivalence checking between SystemC models at different levels of abstraction
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Genetic Programming and Evolvable Machines
Towards accelerating irregular EDA applications with GPUs
Integration, the VLSI Journal
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Integrating formal verification in an online judge for e-Learning logic circuit design
Proceedings of the 43rd ACM technical symposium on Computer Science Education
Verification work reduction methodology in low-power chip implementation
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A SAT-based fitness function for evolutionary optimization of polymorphic circuits
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Verifying refutations with extended resolution
CADE'13 Proceedings of the 24th international conference on Automated Deduction
Automated reencoding of boolean formulas
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Mechanical verification of SAT refutations with extended resolution
ITP'13 Proceedings of the 4th international conference on Interactive Theorem Proving
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