Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
To split or to conjoin: the question in image computation
Proceedings of the 37th Annual Design Automation Conference
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Testing, Verification, and Diagnosis in the Presence of Unknowns
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Permissible functions for multioutput components in combinational logic optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QUBOS: Deciding Quantified Boolean Logic Using Propositional Satisfiability Solvers
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
SAT-Based Techniques in System Synthesis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Quantifier structure in search based procedures for QBFs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
Computation of minimal counterexamples by using black box techniques and symbolic methods
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Solving QBF with combined conjunctive and disjunctive normal form
AAAI'06 Proceedings of the 21st national conference on Artificial intelligence - Volume 1
Clause/term resolution and learning in the evaluation of quantified Boolean formulas
Journal of Artificial Intelligence Research
An AIG-Based QBF-solver using SAT for preprocessing
Proceedings of the 47th Design Automation Conference
Exploiting structure in an AIG based QBF solver
Proceedings of the Conference on Design, Automation and Test in Europe
QBF reasoning on real-world instances
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
The second QBF solvers comparative evaluation
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
sQueezeBF: an effective preprocessor for QBFs based on equivalence reasoning
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Encoding techniques, craig interpolants and bounded model checking for incomplete designs
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Solving quantified boolean formulas with circuit observability don't cares
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Verification of partial designs using incremental QBF solving
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We consider the problem of checking whether a partial implementation can (still) be extended to a complete design which is equivalent to a given full specification.Several algorithms trading off accuracy and computational resources are presented: Starting with a simple 0,1,&KHarX-based simulation, which allows approximate solutions, but is not able to find all errors in the partial implementation, we consider more and more exact methods finally covering all errors detectable in the partial implementation. The exact algorithm reports no error if and only if the current partial implementation conforms to the specification, i.e. it can be extended to a full implementation which is equivalent to the specification.We give a series of experimental results demonstrating the effectiveness and feasibility of the methods presented.