Checking equivalence for partial implementations
Proceedings of the 38th annual Design Automation Conference
On Efficient Error Diagnosis of Digital Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Error Diagnosis of Sequential Circuits Using Region-Based Model
Journal of Electronic Testing: Theory and Applications
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
On combining 01X-logic and QBF
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
Managing verification error traces with bounded model debugging
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Encoding techniques, craig interpolants and bounded model checking for incomplete designs
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Accurate QBF-based test pattern generation in presence of unknown values
Proceedings of the Conference on Design, Automation and Test in Europe
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Improvement of the accuracy of error and fault diagnosis as well as ATPG for IP-based designs is important problems in industry. In this paper, we address these problems when portions of the design may be unspecified. Two approaches to solve these problems have been presented: (1) solving Boolean satisfiability under unknown constraints, and (2) a network modification-based solution. Experimental results on constrained equivalence checking, enhancement of error diagnosis resolution for combinational circuits, and ATPG for IP-based designs have been presented on the ISCAS 85 benchmark and industrial circuits.