Solving the incremental satisfiability problem
Journal of Logic Programming
Checking equivalence for partial implementations
Proceedings of the 38th annual Design Automation Conference
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Pruning Techniques for the SAT-Based Bounded Model Checking Problem
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Compressing BMC Encodings with QBF
Electronic Notes in Theoretical Computer Science (ENTCS)
Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Clause/term resolution and learning in the evaluation of quantified Boolean formulas
Journal of Artificial Intelligence Research
On combining 01X-logic and QBF
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
Bounded model checking with QBF
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
sQueezeBF: an effective preprocessor for QBFs based on equivalence reasoning
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Encoding techniques, craig interpolants and bounded model checking for incomplete designs
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
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SAT solving is an indispensable core component of numerous formal verification tools and has found widespread use in industry, in particular when using it in an incremental fashion, e.g. in Bounded Model Checking (BMC). On the other hand, there are applications, in particular in the area of partial design verification, where SAT formulas are not expressive enough and a description via Quantified Boolean Formulas (QBF) is much more adequate. In this paper we introduce incremental QBF solving and thereby make it usable as a core component of BMC. To do so, we realized an incremental version of the state-of-the-art QBF solver QuBE, allowing for the reuse of learnt information e.g. in the form of conflict clauses and solution cubes. As an application we consider BMC for partial designs (i.e. designs containing so-called blackboxes) and thereby disprove realizability, that is, we prove that an unsafe state is reachable no matter how the blackboxes are implemented. In our experimental analysis, we compare different incremental approaches implemented in our BMC tool. BMC with incremental QBF turns out to be feasible for designs with more than 21,000 gates and 2,700 latches. Significant performance gains over non incremental QBF based BMC can be obtained on many benchmark circuits, in particular when using the so-called backward-incremental approach combined with incremental preprocessing.