Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
Proceedings of the European Conference on Genetic Programming
Designing polymorphic circuits with evolutionary algorithm based on weighted sum method
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
On the completeness of the polymorphic gate set
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable multi-function logic based on graphene P-N junctions
Proceedings of the 47th Design Automation Conference
Genetic Programming and Evolvable Machines
Evolutionary design of gate-level polymorphic digital circuits
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
Redundancy and computational efficiency in Cartesian genetic programming
IEEE Transactions on Evolutionary Computation
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Multifunctional (or polymorphic) gates have been utilized as building blocks for multifunctional circuits that are capable of performing various logic functions under different settings of control signals. In order to effectively synthesize polymorphic circuits, several methods have been developed in the recent years. Unfortunately, the methods are applicable for small circuits only. In this paper, we propose a SAT-based functional equivalence checking algorithm to eliminate the fitness evaluation time which is the most critical overhead for genetic programming-based design and optimization of complex polymorphic circuits. The proposed approach has led to a 20%-40% reduction in gate count with respect to the solutions created using the polymorphic multiplexing.