Delay model for reconfigurable logic gates based on graphene PN-junctions
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions
Proceedings of the Conference on Design, Automation and Test in Europe
A SAT-based fitness function for evolutionary optimization of polymorphic circuits
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Towards new applications of multi-function logic: image multi-filtering
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the operation of the device, leading to reconfigurable multi-functional logic. A device model is derived from carrier transmission probability across the p-n junction for allowing quantitative comparison to CMOS logic. Based on this model, we show that the proposed graphene logic has significant advantages over CMOS gate in terms of delay-power product and signal restoration, while maintaining a similar footprint. Furthermore, the device utilizes a large graphene sheet with minimal patterning, allowing feasible integration with CMOS circuits, for potential CMOS-graphene hybrid circuits.