Evolving hardware with genetic learning: a first step towards building a Darwin machine
Proceedings of the second international conference on From animals to animats 2 : simulation of adaptive behavior: simulation of adaptive behavior
Genetic programming II: automatic discovery of reusable programs
Genetic programming II: automatic discovery of reusable programs
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Genetic Programming III: Darwinian Invention & Problem Solving
Genetic Programming III: Darwinian Invention & Problem Solving
Evolutionary Electronics: Automatic Design of Electronic Circuits and Systems by Genetic Algorithms
Evolutionary Electronics: Automatic Design of Electronic Circuits and Systems by Genetic Algorithms
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Genetic Programming and Evolvable Machines
A Scalable Approach to Evolvable Hardware
Genetic Programming and Evolvable Machines
Image Filter Design with Evolvable Hardware
Proceedings of the Applications of Evolutionary Computing on EvoWorkshops 2002: EvoCOP, EvoIASP, EvoSTIM/EvoPLAN
An Evolutionary Robot Navigation System Using a Gate-Level Evolvable Hardware
ICES '96 Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
Shrinking the Genotype: L-systems for EHW?
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
Hardware Evolution at Function Level
PPSN IV Proceedings of the 4th International Conference on Parallel Problem Solving from Nature
Proceedings of the European Conference on Genetic Programming
A Divide-and-Conquer Approach to Evolvable Hardware
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
The Test Vector Problem and Limitations to Evolving Digital Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Towards the Automatic Design of More Efficient Digital Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Towards Development in Evolvable Hardware
EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
A Taxonomy for artificial embryogeny
Artificial Life
Genetic Programming IV: Routine Human-Competitive Machine Intelligence
Genetic Programming IV: Routine Human-Competitive Machine Intelligence
Evolvable Components: From Theory to Hardware Implementations
Evolvable Components: From Theory to Hardware Implementations
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Towards Development on a Silicon-based Cellular Computing Machine
Natural Computing: an international journal
Introduction to Evolvable Hardware: A Practical Guide for Designing Self-Adaptive Systems (IEEE Press Series on Computational Intelligence)
Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Evolution of synthetic RTL benchmark circuits with predefined testability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Advanced techniques for the creation and propagation of modules in cartesian genetic programming
Proceedings of the 10th annual conference on Genetic and evolutionary computation
On Evolutionary Synthesis of Linear Transforms in FPGA
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
A Developmental Gene Regulation Network for Constructing Electronic Circuits
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Practical and scalable evolution of digital circuits
Applied Soft Computing
An Online EHW Pattern Recognition System Applied to Face Image Recognition
Proceedings of the 2007 EvoWorkshops 2007 on EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog: Applications of Evolutionary Computing
Self modifying cartesian genetic programming: parity
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Applying logic synthesis for speeding up SAT
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
Proceedings of the Conference on Design, Automation and Test in Europe
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Real-world applications of analog and digital evolvable hardware
IEEE Transactions on Evolutionary Computation
Redundancy and computational efficiency in Cartesian genetic programming
IEEE Transactions on Evolutionary Computation
The Automatic Acquisition, Evolution and Reuse of Modules in Cartesian Genetic Programming
IEEE Transactions on Evolutionary Computation
Generalized Disjunction Decomposition for Evolvable Hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Optimality Study of Logic Synthesis for LUT-Based FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 13th annual conference companion on Genetic and evolutionary computation
Coevolution in cartesian genetic programming
EuroGP'12 Proceedings of the 15th European conference on Genetic Programming
GECCO 2012 tutorial: cartesian genetic programming
Proceedings of the 14th annual conference companion on Genetic and evolutionary computation
A module-level three-stage approach to the evolutionary design of sequential logic circuits
Genetic Programming and Evolvable Machines
GECCO 2013 tutorial: cartesian genetic programming
Proceedings of the 15th annual conference companion on Genetic and evolutionary computation
A SAT-based fitness function for evolutionary optimization of polymorphic circuits
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.03 |
We propose to utilize a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimization is then conducted using Cartesian Genetic Programming (CGP) which utilizes a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8% on average with respect to results of the conventional SIS tool.