Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters
EuroGP '01 Proceedings of the 4th European Conference on Genetic Programming
Evolutionary Synthesis of Arithmetic Circuit Structures
Artificial Intelligence Review
Soft Computing - A Fusion of Foundations, Methodologies and Applications
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology)
Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology)
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Virtual reconfigurable circuits for real-world applications of evolvable hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Real-world applications of analog and digital evolvable hardware
IEEE Transactions on Evolutionary Computation
Evolvable Hardware: From Applications to Implications for the Theory of Computation
UC '09 Proceedings of the 8th International Conference on Unconventional Computation
Genetic Programming and Evolvable Machines
Challenges of evolvable hardware: past, present and the path to a promising future
Genetic Programming and Evolvable Machines
Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling
Microprocessors & Microsystems
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In this paper, an evolutionary approach is used to design multiple constant multipliers (MCMs). As these circuits can be composed of adders, subtractors and shifters, they perform a linear transform. An important consequence is that only a single input value is sufficient to completely evaluate a candidate circuit independently of its size and the bit width of the datapath. Proposed method is able to compete with well-optimized heuristics in particular problem instances. This paper also deals with a hardware acceleration of the method in FPGA which provides the speedup of two orders of magnitude in comparison with a conventional PC.