Computer arithmetic algorithms
Computer arithmetic algorithms
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic
ISMVL '03 Proceedings of the 33rd International Symposium on Multiple-Valued Logic
Evolutionary Strategies And Intrinsic Fault Tolerance
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Evolutionary computation: comments on the history and current state
IEEE Transactions on Evolutionary Computation
Automated synthesis of analog electrical circuits by means ofgenetic programming
IEEE Transactions on Evolutionary Computation
Explorations in design space: unconventional electronics designthrough artificial evolution
IEEE Transactions on Evolutionary Computation
Evolving oscillators in silico
IEEE Transactions on Evolutionary Computation
A circuit representation technique for automated circuit design
IEEE Transactions on Evolutionary Computation
Real-world applications of analog and digital evolvable hardware
IEEE Transactions on Evolutionary Computation
Reducing the number of transistors in digital circuits using gate-level evolutionary design
Proceedings of the 9th annual conference on Genetic and evolutionary computation
On Evolutionary Synthesis of Linear Transforms in FPGA
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Automated synthesis of passive analog filters using graph representation
Expert Systems with Applications: An International Journal
Evolutionary design of generic combinational multipliers using development
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
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This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to arithmetic circuit synthesis. Key features of EGG are to employ a graph-based representation of individuals and to manipulate the graph structures directly by evolutionary operations. The potential capability of EGG is demonstrated through experimental synthesis of arithmetic circuits with different levels of abstraction. Design examples include (i) combinational multipliers using word-level arithmetic components (such as parallel counters and parallel shifters), (ii) bit-serial multipliers using bit-level arithmetic components (such as 1-bit full adders and 1-bit registers), and (iii) multiple-valued current-mode arithmetic circuits using transistor-level components (such as current sources and current mirrors).