Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits
IEEE Transactions on Computers
An Optimization Technique for the Design of Multiple Valued PLA's
IEEE Transactions on Computers
Redundant Complex Number Systems
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Evolutionary Synthesis of Arithmetic Circuit Structures
Artificial Intelligence Review
Evolutionary synthesis of arithmetic circuit structures
Artificial intelligence in logic design
Design of system on a chip
| Hi-index | 4.11 |
A description is given of a 32*32-bit signed digit multiplier implemented with multiple-valued, bidirectional, current-mode circuits and based on two-microcomputer complementary metal-oxide-semiconductor technology. The multiplier can perform 32-bit two's-complement multiplication with three-stage SD full adders using a binary-tree addition scheme The effective multiplier size in the chip and the power dissipation are almost half that of the corresponding binary CMOS multiplier. The multiply time is comparable to that of the fastest binary multiplier. These results establish the effectiveness of the technology for future very large scale integration.