Evolutionary synthesis of arithmetic circuit structures

Authors:
Takafumi Aoki;Naofumi Homma;Tatsuo Higuchi
Affiliations:
Graduate School of Information Sciences, Tohoku University, Aoba-yama, Sendai, Japan;Graduate School of Information Sciences, Tohoku University, Aoba-yama, Sendai, Japan and PRESTO, Japan Science and Technology Corporation;Department of Electronics, Tohoku Institute of Technology, Sendai, Japan
Venue:
Artificial intelligence in logic design
Year:
2004

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Abstract

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to arithmetic circuit synthesis. Key features of EGG are to employ a graph-based representation of individuals and to manipulate the graph structures directly by evolutionary operations. The potential capability of EGG is demonstrated through experimental synthesis of arithmetic circuits with different levels of abstraction. Design examples include (i) combinational multipliers using word-level arithmetic components (such as parallel counters and parallel shifters), (ii) bit-serial multipliers using bit-level arithmetic components (such as 1-bit full adders and 1-bit registers), and (iii) multiple-valued current-mode arithmetic circuits using transistor-level components (such as current sources and current mirrors).