Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Approximate reachability with BDDs using overlapping projections
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient equivalence checking of multi-phase designs using retiming
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Robust latch mapping for combinational equivalence checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
To split or to conjoin: the question in image computation
Proceedings of the 37th Annual Design Automation Conference
Least fixpoint approximations for reachability analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Exploiting Structural Similarities in a BDD-Based Verification Method
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Exploiting Functional Dependencies in Finite State Machine Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
DAC '81 Proceedings of the 18th Design Automation Conference
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Formal verification of a PowerPC microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Equivalence checking of combinational circuits using Boolean expression diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient filter-based approach for combinational verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational equivalence checking for threshold logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Mutation-based test case generation for simulink models
FMCO'09 Proceedings of the 8th international conference on Formal methods for components and objects
Test-case generation for embedded simulink via formal concept analysis
Proceedings of the 48th Design Automation Conference
Integrating formal verification in an online judge for e-Learning logic circuit design
Proceedings of the 43rd ACM technical symposium on Computer Science Education
Tightening test coverage metrics: a case study in equivalence checking using k-induction
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
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This chapter covers the problem of deciding functional equivalence of two design descriptions. We focus our presentation on the most commonly used form of equivalence checking, which compares the input/output behavior of two deterministic design models. We define the fundamental problem of equivalence checking and outline a general approach for its solution. Because of the broad practical relevance, we pay special attention to the problem of combinational equivalence checking and discuss various methods to make it scalable and robust for large designs. Furthermore, we outline key techniques for general sequential equivalence checking and present some basic methods to improve their performance.