Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Regular layout generation of logically optimized datapaths
Proceedings of the 1997 international symposium on Physical design
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
On equivalence checking and logic synthesis of circuits with a common specification
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A BDD-based verification method for large synthesized circuits
Integration, the VLSI Journal
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