Efficient equivalence checking of multi-phase designs using retiming

Combinational and sequential equivalence checking

Logic Synthesis and Verification

Register Transformations with Multiple Clock Domains

CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

Transformation-Based Verification Using Generalized Retiming

CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification

Timing optimization by replacing flip-flops to latches

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis

Proceedings of the 2009 Asia and South Pacific Design Automation Conference