Multi-level synthesis for safe replaceability
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Latch Redundancy Removal Without Global Reset
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Design replacements for sequential circuits
Design replacements for sequential circuits
Efficient equivalence checking of multi-phase designs using retiming
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Implicit enumeration of strongly connected components
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
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Finding the set of steady states of a machine has applications in formal verification, sequential synthesis and ATPG. Existing techniques assume the presence of a designated set of initial states which is impractical in a real design environment. The set of steady state of a design is defined by the terminally strongly connected components (tSCCs) of the underlying state transition graph (STG). We show that multiple tSCCs and non-terminal SCCs need to be handled in a real design environment especially for verification. We present a fully implicit algorithm to find the steady states of a machine without any knowledge of initial states. We demonstrate the utility of our algorithm by applying it to FSM equivalence checking.