Recurrence equations and the optimization of synchronous logic circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Binary decision diagrams and their applications to implicit enumeration techniques in logic synthesis
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Redundancy Identification and Removal Based on Implicit State Enumeration
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
The Verifiacation Problem for Safe Replaceability
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Exploiting power-up delay for sequential optimization
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An implicit algorithm for finding steady states and its application to FSM verification
DAC '98 Proceedings of the 35th annual Design Automation Conference
Analysis of composition complexity and how to obtain smaller canonical graphs
Proceedings of the 37th Annual Design Automation Conference
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Data driven power optimization of sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Verifying sequential equivalence using ATPG techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic Synthesis and Verification
Applied Boolean Equivalence Verification and RTL Static Sign-Off
IEEE Design & Test
Sequential optimization in the absence of global reset
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compositional verification of retiming and sequential optimizations
Proceedings of the 45th annual Design Automation Conference
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We describe the condition that a sequential digital design is a safe replacement for an existing design without making any assumptions about a known initial state of the design or about its environment. We formulate a safe replacement condition which guarantees that if an original design is replaced by a new design, the interacting environment cannot detect the change by observing the input-output behavior of the new design; conversely, if a replacement design does not satisfy our condition an environment can potentially detect the replacement (in this sense the replacement is potentially unsafe). Our condition allows simplification of the state transition diagram of an original design. We use the safe replacement condition to derive a sequential resynthesis method for area reduction of gate-level designs. We have implemented our resynthesis algorithm and we report experimental results.