Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On the temporal equivalence of sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Multi-level synthesis for safe replaceability
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
IEEE Transactions on Computers
Using combinational verification for sequential circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A practical approach to multiple-class retiming
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
TRANS: efficient sequential verification of loop-free circuits
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Post-reboot Equivalence and Compositional Verification of Hardware
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Proceedings of the conference on Design, automation and test in Europe
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory of safe replacements for sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Once a design is both retimed and sequentially optimized, sequential equivalence verification becomes very hard since retiming breaks the equivalence of the retimed sub-blocks although the design equivalence is preserved. This paper presents a novel compositional algorithm to verify sequential equivalence of large designs that are not only retimed but also optimized sequentially and combinationally. With a new notion of conditional equivalence in the presence of retiming, the proposed compositional algorithm performs hierarchical verification by checking whether each sub-block is conditionally equivalent, then checking whether the conditions are justified on their parent block by temporal equivalence. This is the first compositional algorithm handling both retiming and sequential optimizations hierarchically. The proposed approach is completely automatic and orthogonal to any existing sequential equivalence checker. The experimental results show that the proposed algorithm can handle large industrial designs that cannot be verified by the existing methods on sequential equivalence checking.