Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
On the over-specification problem in sequential ATPG algorithms
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level synthesis for safe replaceability
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On test set preservation of retimed circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective safety property checking using simulation-based sequential ATPG
Proceedings of the 39th annual Design Automation Conference
Verifying the correctness of FPGA logic synthesis algorithms
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Principles of Sequential-Equivalence Verification
IEEE Design & Test
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
| Hi-index | 0.00 |
In this paper we address the problem of verifying the equivalence of two sequential circuits. State-of-the-art sequential optimization techniques such as retiming and sequential redundancy removal can handle designs with up to hundreds or even thousands of flip-flops. However, the BDD-based approaches for verifying sequential equivalence can easily run into memory explosion for such designs. In an attempt to handle larger circuits, we modify test pattern-generation techniques for verification. The suggested approach utilizes the popular efficient backward-justification technique used in most sequential ATPG programs. We present several techniques to enhance the efficiency of this approach by (1) identifying equivalent flip-flop pairs using an induction-based algorithm, and (2) generalizing the idea of exploring the structural similarity between circuits to perform verification in stages. This ATPG-based framework is suitable for verifying circuits either with or without a reset state. In order to extend this approach to verify retimed circuits, we introduce a delay-compensation-based algorithm for preprocessing the circuits. The experimental results of verifying the correctness of circuits after sequential redundancy removal and retiming with up to several hundred flip-flops are presented.