A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
Verifying sequential equivalence using ATPG techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
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