AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Verifying sequential equivalence using ATPG techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
This paper describes novel contributions to the problem of sequential equivalence checking. We address industrial setups, where the design of VLSI chips typically requires checking the equivalence of an RTL model (the specification) and a gate level optimized circuit (the implementation). Due to the size of the overall problem, compositionality is required. The circuit must be resetable, but the reset state is not yet known when equivalence checking is performed. In this paper we discuss the conditions under which decomposed proofs of equivalence are able to infer the equivalence of the full design. Our main contributions with respect to the state of the art in this field are: (1) discussing compositionality given a 3-valued initialization scheme, (2) accepting decompositions with overlapping partitions.