Efficient equivalence checking of multi-phase designs using retiming
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Model checking
Using complete-1-distinguishability for FSM equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Inductive equivalence checking under retiming and resynthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming and Resynthesis: A Complexity Perspective
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Iterative retiming and resynthesis is a powerful way to optimize sequential circuits but its massive adoption has been hampered by the hardness of verification. This paper tackles the problem of retiming and resynthesis equivalence checking on a pair of circuits. For this purpose we define the Complete-k-Distinguishability (C-k-D) property for any natural number k based on C-1-D. We show how the equivalence checking problem can be simplified if the circuits satisfy this property and prove that the method is complete for any number of retiming and resynthesis steps. We also provide a way to enforce C-k-D on the circuits without restricting the optimization power of retiming and resynthesis or increasing their complexity. Experimental results demonstrate that enforcing C-k-D property can speed up the verification process.