Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Model checking
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Formal Verification of Square Root Algorithms
Formal Methods in System Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
A static analyzer for large safety-critical software
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Interpretation of IEEE-854 Floating-Point Standard and Definition in the HOL System
Interpretation of IEEE-854 Floating-Point Standard and Definition in the HOL System
Generating Tests from Counterexamples
Proceedings of the 26th International Conference on Software Engineering
Checking consistency of C and Verilog using predicate abstraction and induction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
AutoMOTGen: Automatic Model Oriented Test Generator for Embedded Control Systems
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
FShell: Systematic Test Case Generation for Dynamic Analysis and Measurement
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Interactive Fault Localization Techniques in a Spreadsheet Environment
IEEE Transactions on Software Engineering
VMCAI '09 Proceedings of the 10th International Conference on Verification, Model Checking, and Abstract Interpretation
A theory of mutations with applications to vacuity, coverage, and fault tolerance
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Efficient mutation testing by checking invariant violations
Proceedings of the eighteenth international symposium on Software testing and analysis
Translation Validation: From Simulink to C
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Automatic Test Generation for Coverage Analysis Using CBMC
Computer Aided Systems Theory - EUROCAST 2009
Coverage in interpolation-based model checking
Proceedings of the 47th Design Automation Conference
An Analysis and Survey of the Development of Mutation Testing
IEEE Transactions on Software Engineering
A theory of predicate-complete test coverage and generation
FMCO'04 Proceedings of the Third international conference on Formal Methods for Components and Objects
Tool for translating simulink models into input language of a model checker
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Model-based safety analysis of simulink models using SCADE design verifier
SAFECOMP'05 Proceedings of the 24th international conference on Computer Safety, Reliability, and Security
Seamless testing for models and code
FASE'11/ETAPS'11 Proceedings of the 14th international conference on Fundamental approaches to software engineering: part of the joint European conferences on theory and practice of software
Test-case generation for embedded simulink via formal concept analysis
Proceedings of the 48th Design Automation Conference
Tightening test coverage metrics: a case study in equivalence checking using k-induction
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
Analysis and testing of matlab simulink models: a systematic mapping study
Proceedings of the 2013 International Workshop on Joining AcadeMiA and Industry Contributions to testing Automation
System level formal verification via model checking driven simulation
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Coverage-based trace signal selection for fault localisation in post-silicon validation
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Incremental language inclusion checking for networks of timed automata
FORMATS'13 Proceedings of the 11th international conference on Formal Modeling and Analysis of Timed Systems
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The Matlab/Simulink language has become the standard formalism for modeling and implementing control software in areas like avionics, automotive, railway, and process automation. Such software is often safety critical, and bugs have potentially disastrous consequences for people and material involved. We define a verification methodology to assess the correctness of Simulink programs by means of automated test-case generation. In the style of fault- and mutation-based testing, the coverage of a Simulink program by a test suite is defined in terms of the detection of injected faults. Using bounded model checking techniques, we are able to effectively and automatically compute test suites for given fault models. Several optimisations are discussed to make the approach practical for realistic Simulink programs and fault models, and to obtain accurate coverage measures.