Theoretical Computer Science
Timing verification by successive approximation
Information and Computation
Bounded Model Checking for Timed Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Verification of Timed Automata via Satisfiability Checking
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Conformance testing for real-time systems
Formal Methods in System Design
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Model based testing with labelled transition systems
Formal methods and testing
UML in action: a two-layered interpretation for testing
ACM SIGSOFT Software Engineering Notes
An Evaluation of SMT-Based Schedule Synthesis for Time-Triggered Multi-hop Networks
RTSS '10 Proceedings of the 2010 31st IEEE Real-Time Systems Symposium
Mutation-based test case generation for simulink models
FMCO'09 Proceedings of the 8th international conference on Formal methods for components and objects
Test-case generation for embedded simulink via formal concept analysis
Proceedings of the 48th Design Automation Conference
Fault-based generation of test cases from UML-Models: approach and some experiences
SAFECOMP'11 Proceedings of the 30th international conference on Computer safety, reliability, and security
Exact incremental analysis of timed automata with an SMT-solver
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
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Checking the language inclusion between two models is a fundamental problem arising in application areas such as formal verification or refinement in top-down design. We propose an incremental procedure for checking the language inclusion between two real-time specifications, modeled as networks of deterministic timed automata, where the two specifications are equivalent up to one component. For such classes of systems we aim to improve the efficiency of the language inclusion check by exploiting the compositional nature of the problem and avoiding the explicit parallel composition of the timed automata in the network. We first develop a generic procedure that gives freedom to specific implementation choices. We then propose an instantiation of the procedure that is based on bounded model checking techniques. We illustrate the application of our approach in a case study and discuss promising experimental results.