Characterizing finite Kripke structures in propositional temporal logic
Theoretical Computer Science - International Joint Conference on Theory and Practice of Software Development, P
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
On the Use of a High-Level Fault Model to Check Properties Incompleteness
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Flow control and micro-architectural mechanisms for extending the performance of interconnection networks
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Estimating functional coverage in bounded model checking
Proceedings of the conference on Design, automation and test in Europe
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
Branching vs. linear time: semantical perspective
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
The role of mutation analysis for property qualification
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Coverage in interpolation-based model checking
Proceedings of the 47th Design Automation Conference
Mutation-based test case generation for simulink models
FMCO'09 Proceedings of the 8th international conference on Formal methods for components and objects
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test-case generation for embedded simulink via formal concept analysis
Proceedings of the 48th Design Automation Conference
Incremental formal verification of hardware
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Tightening test coverage metrics: a case study in equivalence checking using k-induction
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
A guiding coverage metric for formal verification
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
From model checking to model measuring
CONCUR'13 Proceedings of the 24th international conference on Concurrency Theory
| Hi-index | 0.00 |
The quality of formal specifications and the circuits they are written for can be evaluated through checks such as vacuity and coverage. Both checks involve mutations to the specification or the circuit implementation. In this context, we study and prove properties of mutations to finite-state systems. Since faults can be viewed as mutations, our theory of mutations can also be used in a formal approach to fault injection. We demonstrate theoretically and with experimental results how relations and orders amongst mutations can be used to improve specifications and reason about coverage of fault tolerant circuits.