Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Incremental Verification by Abstraction
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Coverage metrics for formal verification
International Journal on Software Tools for Technology Transfer (STTT) - A View from Formal Methods 2003 (pp 301-354); Special Section on Recent Advances in Hardware Verification (pp 355-447)
Automated Extraction of Inductive Invariants to Aid Model Checking
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
A theory of mutations with applications to vacuity, coverage, and fault tolerance
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Strengthening model checking techniques with inductive invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coverage in interpolation-based model checking
Proceedings of the 47th Design Automation Conference
Speeding up model checking by exploiting explicit and hidden verification constraints
Proceedings of the Conference on Design, Automation and Test in Europe
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Software model checking via IC3
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Incremental, inductive CTL model checking
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Using cubes of non-state variables with property directed reachability
Proceedings of the Conference on Design, Automation and Test in Europe
Precision reuse for efficient regression verification
Proceedings of the 2013 9th Joint Meeting on Foundations of Software Engineering
Thread-based multi-engine model checking for multicore platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Formal verification is a reliable and fully automatic technique for proving correctness of hardware designs. Its main drawback is the high complexity of verification, and this problem is especially acute in regression verification, where a new version of the design, differing from the previous version very slightly, is verified with respect to the same or a very similar property. In this paper, we present an efficient algorithm for incremental verification, based on the ic3 algorithm, that uses stored information from the previous verification runs in order to improve the complexity of re-verifying similar designs on similar properties. Our algorithm applies both to the positive and to the negative results of verification (that is, both when there is a proof of correctness and when there is a counterexample). The algorithm is implemented and experimental results show improvement of up to two orders of magnitude in running time, compared to full verification.