Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Accelerated verification of RTL assertions based on satisfiability solvers
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Boosting the role of inductive invariants in model checking
Proceedings of the conference on Design, automation and test in Europe
Algorithms for approximate FSM traversal based on state space decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
Property-specific sequential invariant extraction for SAT-based unbounded model checking
Proceedings of the International Conference on Computer-Aided Design
Incremental formal verification of hardware
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Thread-based multi-engine model checking for multicore platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper describes optimized techniques to efficiently compute and reap benefits from inductive invariants within satisfiability (SAT)-based model checking. We address sequential circuit verification and consider both equivalences and implications between pairs of nodes in the logic networks. First, we present a very efficient dynamic procedure, based on equivalence classes and incremental SAT, specifically oriented to reduce the set of checked invariants. Then, we show how to effectively integrate the computation of inductive invariants within state-of-the-art SAT-based model-checking procedures. Experiments (on more than 600 designs) show the robustness of our approach on verification instances on which stand-alone techniques fail.