Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Stepping forward with interpolants in unbounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Boosting the role of inductive invariants in model checking
Proceedings of the conference on Design, automation and test in Europe
Boosting interpolation with dynamic localized abstraction and redundancy removal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Strengthening model checking techniques with inductive invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Partitioning interpolant-based verification for effective unbounded model checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
| Hi-index | 0.00 |
In this paper a non-canonical circuit-based state set representation is used to efficiently perform quantifier elimination. The novelty of this approach lies in adapting equivalence checking and logic synthesis techniques, to the goal of compacting circuit based state set representations resulting from existential quantification. The method can be efficiently combined with other verification approaches such as inductive and SAT-based pre-image verifications.