High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
DAG-aware circuit compression for formal verification
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SAT-based sequential depth computation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Interpolant Learning and Reuse in SAT-Based Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Boosting the role of inductive invariants in model checking
Proceedings of the conference on Design, automation and test in Europe
Boosting interpolation with dynamic localized abstraction and redundancy removal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Trading-off SAT search and variable quantifications for effective unbounded model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Approximation refinement for interpolation-based model checking
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Improvements to the implementation of interpolant-based model checking
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
Efficient implementation of property directed reachability
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Thread-based multi-engine model checking for multicore platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Interpolant-based model checking has been shown to be effective on large verification instances, as it efficiently combines automated abstraction and reachability fixed-point checks. On the other hand, methods based on variable quantification have proved their ability to remove free inputs, thus projecting the search space over state variables. In this paper, we propose an integrated approach which combines the abstraction power of interpolation with techniques that rely on and-inverter graph (AIG) and/or binary decision diagram (BDD) representations of states, directly supporting variable quantification and fixed-point checks. The underlying idea of this combination is to adopt AIG or BDD-based quantifications to limit and restrict the search space and the complexity of the interpolant-based approach. The exploited strategies, most of which are individually well known, are integrated with a new flavor, specifically designed to improve their effectiveness on difficult verification instances. Experimental results, specifically oriented to hard-to-solve verification problems, show the robustness of our approach.