Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Efficient and Effective Redundancy Removal for Million-Gate Circuits
Proceedings of the conference on Design, automation and test in Europe
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Improvements to the implementation of interpolant-based model checking
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Search pruning techniques in SAT-based branch-and-bound algorithms for the binate covering problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Model checking with Boolean Satisfiability
Journal of Algorithms
Automated abstraction by incremental refinement in interpolant-based model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Invariant-strengthened elimination of dependent state elements
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Trading-off SAT search and variable quantifications for effective unbounded model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Journal of Electronic Testing: Theory and Applications
Approximation refinement for interpolation-based model checking
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Efficient interpolant generation in satisfiability modulo theories
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Efficient generation of craig interpolants in satisfiability modulo theories
ACM Transactions on Computational Logic (TOCL)
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
Intertwined forward-backward reachability analysis using interpolants
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Lemma localization: a practical method for downsizing SMT-interpolants
Proceedings of the Conference on Design, Automation and Test in Europe
A counterexample-guided interpolant generation algorithm for SAT-based model checking
Proceedings of the 50th Annual Design Automation Conference
Thread-based multi-engine model checking for multicore platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient generation of small interpolants in CNF
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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This paper addresses SAT-based Unbounded Model Checking based on Craig Interpolants. This recently introduced methodology is often able to outperform BDDs and other SAT-based techniques on large verification instances. Based on refutation proofs generated by SAT solvers, interpolants provide compact circuit representations of state sets, and abstract away several details non relevant for proofs. We propose three main contributions, aimed at controlling interpolant size and traversal depth. First of all, we introduce interpolant-based dynamic abstraction to reduce the support of the computed interpolant. Second, we propose new advances in interpolant compaction by redundancy removal. Both techniques rely on an effective application of the incremental SAT paradigm. Finally, we also introduce interpolant computation exploiting circuit quantification, instead of SAT refutation proofs. Experimental results are specifically oriented to prove properties, rather than disproving them (bug hunting). They show how the methodology is able to extend the applicability of interpolant based Model Checking to larger and deeper verification instances.