Logic synthesis
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Some approaches to best-match file searching
Communications of the ACM
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Principles of Sequential-Equivalence Verification
IEEE Design & Test
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Automatic generalized phase abstraction for formal verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Node Mergers in the Presence of Don't Cares
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Fast detection of node mergers using logic implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Node addition and removal in the presence of don't cares
Proceedings of the 47th Design Automation Conference
Sequential logic synthesis using symbolic bi-decomposition
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable liveness checking via property-preserving transformations
Proceedings of the Conference on Design, Automation and Test in Europe
Fast node merging with don't cares using logic implications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
This paper presents a new type of sequential technology independent synthesis. Building on the previous notions of combinational observability and sequential equivalence, sequential observability is introduced and discussed. By considering both the sequential nature of the design and observability simultaneously, better results can be obtained than with either algorithm alone. The experimental results show that this method can reduce the technology-independent gate count up to 10% more than the previously best known synthesis techniques.