A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Node Mergers in the Presence of Don't Cares
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Merging nodes under sequential observability
Proceedings of the 45th annual Design Automation Conference
Fast detection of node mergers using logic implications
Proceedings of the 2009 International Conference on Computer-Aided Design
On rewiring and simplification for canonicity in threshold logic circuits
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.03 |
Node merging is a popular and effective logic restructuring technique that has recently been applied to minimize logic circuits. However, in the previous satisfiability (SAT)-based methods, the search for node mergers required trial-and-error validity checking of a potentially large set of candidate mergers. Here, we propose a new method, which directly identifies node mergers using logic implications without any SAT solving calls. Although the efficiency benefits of the method come at the expense of quality, we further engage the redundancy removal and the wire replacement techniques to enhance its quality. The experimental results show that the proposed optimization method achieves approximately 46 times the speedup while possessing a competitive capability of circuit minimization compared to the state-of-the-art method.