Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Symbolic manipulation of Boolean functions using a graphical representation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Effective safety property checking using simulation-based sequential ATPG
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video
Computer Standards & Interfaces
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We present a promising formal verification methodology based on the inductive approach using the imPROVE-HDL tool. This methodology is dedicated for RTL IPs or IP-based digital/logic hardware designs to prove the correctness of their temporal properties related to the control-dominated architecture model. Each temporal property can be checked through the IP interface where all properties have to be proved or disproved. We developed a new methodology to generate the appropriate environment of the IP interface according to the design context (master, slave, arbiter and decoder) before starting the verification of all properties one by one. When all temporal properties are verified, we generate some test sequences that contain a complex scenario to check the compatibility between all properties. We implemented our methodology to generate the appropriate environment and applied the inductive approach to verify various properties of two real IP designs using the imPROVE-HDL tool developed by TNI-Valiosys. The first design is an RTL IP-based digital hardware dedicated for real time video processing, where the second one performs an AHB to AHB Bridge. On these designs, we successfully proved few properties and discovered a design violation.