ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
Fast illegal state identification for improving SAT-based induction
Proceedings of the 43rd annual Design Automation Conference
A novel formal verification approach for RTL hardware IP cores
Computer Standards & Interfaces
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We present a novel technique of improving the SAT-basedBounded Model Checking, by inducing powerful sequential signalcorrelations (crossing time-frame boundaries) into the originalCNF formula of the unrolled circuit. A quick preprocessing on thecircuit-under-verification, builds a large set of direct and indirectsequential implications. The non-trivial implications (spanningmultiple time-frames) are converted into two-literal clauses. Theseclauses are quickly replicated throughout the unrolled sequentialcircuit, and appended to the existing CNF database. The addedclauses prune the overall search space of SAT-solver engine andprovide correlation among the different variables, which enhancesthe Boolean Constraint Propagation (BCP). Experimental Resultsfor checking difficult instances of random safety properties onISCAS'89 benchmark circuits show that more than 148x speedupcan be achieved over the conventional approach.