IBM Systems Journal
A dual watermarking technique for images
MULTIMEDIA '99 Proceedings of the seventh ACM international conference on Multimedia (Part 2)
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Protection of wavelet-based watermarking systems using filter parametrization
Signal Processing - Special section: Security of data hiding technologies
An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A VLSI architecture for watermarking in a secure still digital camera (S2DC) design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel formal verification approach for RTL hardware IP cores
Computer Standards & Interfaces
Hardware implementation perspectives of digital video watermarking algorithms
IEEE Transactions on Signal Processing
Blind quality assessment system for multimedia communications using tracing watermarking
IEEE Transactions on Signal Processing
Watermarking of MPEG-4 video objects
IEEE Transactions on Multimedia
DCT-based watermarking for video
IEEE Transactions on Consumer Electronics
The JPEG2000 still image coding system: an overview
IEEE Transactions on Consumer Electronics
Attacks on digital watermarks: classification, estimation based attacks, and benchmarks
IEEE Communications Magazine
Line-based, reduced memory, wavelet image compression
IEEE Transactions on Image Processing
Evaluation of design alternatives for the 2-D-discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
A Semi-Fragile Lossless Digital Watermarking Scheme Based on Integer Wavelet Transform
IEEE Transactions on Circuits and Systems for Video Technology
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This paper describes an efficient hardware architecture of 2D-Scan-based-Wavelet watermarking for image and video. The potential application for this architecture includes broadcast monitoring of video sequences for High Definition Television (HDTV) and DVD protection and access control. The proposed 2D design allows even distribution of the processing load onto a set of filters, with each set performing the calculation for one dimension according to the scan-based process. The video protection is achieved by the insertion of watermarks bank within the middle frequency of wavelet coefficients related to video frames by their selective quantization. The 2-D DWT is applied for both video stream and watermark in order to make the watermarking scheme robust and perceptually invisible. The proposed architecture has a very simple control part, since the data are operated in a row-column-slice fashion. This organization reduces the requirement of on-chip memory. In addition, the control unit selects which coefficient to pass to the low-pass and high-pass filters. The on-chip memory will be small as compared to the input size since it depends solely on the filter sizes. Due to the pipelining, all filters are utilized for 100% of the time except during the start-up and wind-down times. The major contribution of this research is towards the selection of appropriate real time watermarking scheme and performing a trade-off between the algorithmic aspects of our proposed watermarking scheme and the hardware implementation technique. The hardware architecture is designed, as a watermarking based IP core with the Avalon interface related to NIOS embedded processor, and tested in order to evaluate the performance of our proposed watermarking algorithm. This architecture has been implemented on the Altera Stratix-II Field Programmable Gate Array (FPGA) prototyping board. Experimental results are presented to demonstrate the capability of the proposed watermarking system for real time applications and its robustness against malicious attacks.