A VLSI architecture for watermarking in a secure still digital camera (S2DC) design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Content-adaptive digital music watermarking based on music structure analysis
ACM Transactions on Multimedia Computing, Communications, and Applications (TOMCCAP)
Guest Editorial: Circuits and systems for real-time security and copyright protection of multimedia
Computers and Electrical Engineering
Hardware assisted watermarking for multimedia
Computers and Electrical Engineering
Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video
Computer Standards & Interfaces
A secure digital camera architecture for integrated real-time digital rights management
Journal of Systems Architecture: the EUROMICRO Journal
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
International Journal of Electronic Security and Digital Forensics
Real-time perceptual watermarking architectures for video broadcasting
Journal of Systems and Software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An ASIC implementation of a low power robust invisible watermarking processor
Journal of Systems Architecture: the EUROMICRO Journal
FPGA based implementation of an invisible-robust image watermarking encoder
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
Journal of Signal Processing Systems
Hi-index | 35.68 |
We consider hardware implementation aspects of the digital watermarking problem through the implementation of a well-known video watermarking algorithm called just another watermarking system (JAWS); we discuss the time and area constraints that must be satisfied by a successful hardware implementation. A hardware architecture that implements the algorithm under the constraints is then proposed. The architecture is analyzed to gain an understanding of the relationships between algorithmic features and implementation cost. Some general findings of this work that can be applied toward making algorithmic developments more amenable to hardware implementation are finally presented.