Communications of the ACM
Protecting digital media content
Communications of the ACM
A Secure, Robust Watermark for Multimedia
Proceedings of the First International Workshop on Information Hiding
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Secure Data Hiding Scheme for Two-Color Images
ISCC '00 Proceedings of the Fifth IEEE Symposium on Computers and Communications (ISCC 2000)
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A VLSI architecture for watermarking in a secure still digital camera (S2DC) design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust spatial image watermarking using progressive detection
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 2001. on IEEE International Conference - Volume 03
FPGA based implementation of an invisible-robust image watermarking encoder
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
Hardware implementation perspectives of digital video watermarking algorithms
IEEE Transactions on Signal Processing
Pattern-Based Data Hiding for Binary Image Authentication by Connectivity-Preserving
IEEE Transactions on Multimedia
VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking
IEEE Transactions on Consumer Electronics
Attacks on digital watermarks: classification, estimation based attacks, and benchmarks
IEEE Communications Magazine
IEEE Journal on Selected Areas in Communications
Secure spread spectrum watermarking for multimedia
IEEE Transactions on Image Processing
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Digital watermarking is the process of hiding information into a digital signal to authenticate the contents of digital data. There are number of watermarking algorithm implemented in software and few in hardware. This paper discusses the implementation of robust invisible binary image watermarking algorithm in Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC) using connectivity preserving criteria. The algorithm is processed in spatial domain. The algorithm is prototyped in (i) XILINX FPGA (ii) 130nm ASIC. The algorithm is tested in Virtex-E (xcv50e-8-cs144) FPGA and implemented in an ASIC.