Adaptive block watermarking and its SOC implementation based on JPEG2000 DWT
SSIP'07 Proceedings of the 7th WSEAS International Conference on Signal, Speech and Image Processing
Hardware assisted watermarking for multimedia
Computers and Electrical Engineering
A secure digital camera architecture for integrated real-time digital rights management
Journal of Systems Architecture: the EUROMICRO Journal
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
International Journal of Electronic Security and Digital Forensics
An ASIC implementation of a low power robust invisible watermarking processor
Journal of Systems Architecture: the EUROMICRO Journal
FPGA based implementation of an invisible-robust image watermarking encoder
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
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Watermarking is the process that embeds data calleda watermark into a multimedia object for its copyrightprotection. The digital watermarks can be visible to aviewer on careful inspection or completely invisible andcannot be easily recovered without an appropriate decodingmechanism. Digital image watermarking is a computationallyintensive task and can be speeded up sigificantly byimplementing in hardware. In this work, we describe a newVLSI architecture for implementing two different visible watermarkingschemes for images. The proposed hardware caninsert on-the-fly either one or both watermarks into an imagedepending on the application requirement. The proposedcircuit can be integrated into any existing digital still cameraframework. First, separate architectures are derived for thetwo watermarking schemes and then integrated into a unifiedarchitecture. A prototype CMOS VLSI chip was designedand verified implementing the proposed architecture and reportedin this paper. To our knowledge, this is the first VLSIarchitecture for implementing visible watermarking schemes.