Protecting digital media content
Communications of the ACM
Information Hiding Techniques for Steganography and Digital Watermarking
Information Hiding Techniques for Steganography and Digital Watermarking
A Secure, Robust Watermark for Multimedia
Proceedings of the First International Workshop on Information Hiding
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA based implementation of an invisible-robust image watermarking encoder
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
Hardware implementation perspectives of digital video watermarking algorithms
IEEE Transactions on Signal Processing
Pattern-Based Data Hiding for Binary Image Authentication by Connectivity-Preserving
IEEE Transactions on Multimedia
VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking
IEEE Transactions on Consumer Electronics
Attacks on digital watermarks: classification, estimation based attacks, and benchmarks
IEEE Communications Magazine
IEEE Journal on Selected Areas in Communications
Secure spread spectrum watermarking for multimedia
IEEE Transactions on Image Processing
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Digital watermarking is the process of embedding data called watermark into a multimedia object so that it can be detected or extracted later to make an assertion about the object. Several software implementations of watermarking algorithms are available, but very few attempts have been made for hardware implementation. The objective of this research paper is to implement ''low power robust invisible binary image watermarking processor'' in an Application Specific Integrated Circuit (ASIC) using Hardware Description Language (HDL). An 8-bit processor has been used since it consumes less power than other higher order bit (16-bit, 32-bit, etc.) processors. The proposed invisible watermarking algorithm is implemented in spatial domain. The proposed algorithm is prototyped (i) using XILINX FPGA (ii) using ASIC. To the best of our knowledge this is the first low power binary image watermarking processor implemented in ASIC which uses 8-bit processor with no limitation on input size. The algorithm is tested in Virtex E (xcv50e-8-cs144) Field Programmable Gate Arrays (FPGA) and implemented in an ASIC.