Hardware assisted watermarking for multimedia
Computers and Electrical Engineering
International Journal of Electronic Security and Digital Forensics
An ASIC implementation of a low power robust invisible watermarking processor
Journal of Systems Architecture: the EUROMICRO Journal
FPGA based implementation of an invisible-robust image watermarking encoder
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
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A VLSI architecture for the embedded zerotree wavelet (EZW) algorithm is presented that enables real-time scalable image coding. The breadth-first bottom-up search method is adopted in scanning the wavelet coefficients in the ancestor-descendant tree hierarchy in order to easily locate the parent-children relationship and to increase the processing speed. The symbols generated in the significance mapping (SMAP) process and those in the successive approximation quantization (SAQ) process are encoded independently. Compared to previously proposed architectures, our design leads to fewer transmitted bits and thus alleviates the communication overhead without sacrificing peak-signal-noise-ratio (PSNR). In addition, a simple progressive digital watermarking scheme is included in the EZW coder for purpose of copyright protection