A VLSI architecture for visible watermarking in a secure still digital camera (S2DC) design (corrected)

Authors:
Saraju P. Mohanty;Nagarajan Ranganathan;Ravi K. Namballa
Affiliations:
Department of Computer Science and Engineering, University of North Texas, Denton, TX;Department of Computer Science and Engineering, University of South Florida, Tampa, FL;Aeolus Systems LLC, Clearwater, FL
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can either be visible or invisible. A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a viewer on a careful inspection. The invisible watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed, and it can be recovered only with an appropriate decoding mechanism. This paper presents a new very large scale integration (VLSI) architecture for implementing two visible digital image watermarking schemes. The proposed architecture is designed to aim at easy integration into any existing digital camera framework. To the authors' knowledge, this is the first VLSI architecture for implementing visible watermarking schemes. A prototype chip consisting of 28 469 gates is implemented using 0.35- m technology, which consumes 6.9-mW power while operating at 292 MHz.