Protecting digital media content
Communications of the ACM
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2002 conference on Applications, technologies, architectures, and protocols for computer communications
The first 50 years of electronic watermarking
EURASIP Journal on Applied Signal Processing - Emerging applications of multimedia data hiding
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MPEG Video Encryption Algorithms
Multimedia Tools and Applications
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
I Want My IPTV: Internet Protocol Television Predicted a Winner
IEEE Distributed Systems Online
IEEE MultiMedia
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Using Level Restoring Method for Dual Supply Voltage
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Algorithm 851: CG_DESCENT, a conjugate gradient method with guaranteed descent
ACM Transactions on Mathematical Software (TOMS)
A VLSI architecture for watermarking in a secure still digital camera (S2DC) design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Single-Cycle Multi-Match Packet Classification Engine Using TCAMs
HOTI '06 Proceedings of the 14th IEEE Symposium on High-Performance Interconnects
Design of mixed gates for leakage reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
IntellBatt: towards smarter battery design
Proceedings of the 45th annual Design Automation Conference
A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO
Microelectronics Journal
Hardware assisted watermarking for multimedia
Computers and Electrical Engineering
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A PVT aware accurate statistical logic library for high-κ metal-gate nano-CMOS
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Hardware implementation perspectives of digital video watermarking algorithms
IEEE Transactions on Signal Processing
The battle for broadband [Internet protocol television]
IEEE Spectrum
The MPEG-4 video standard verification model
IEEE Transactions on Circuits and Systems for Video Technology
Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Nano-CMOS thermal sensor design optimization for efficient temperature measurement
Integration, the VLSI Journal
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Power dissipation is a major bottleneck for emerging applications, such as implantable systems, digital cameras, and multimedia processors. Each of these applications is essentially designed as an Analog/Mixed-Signal System-on-a-Chip (AMS-SoC). These AMS-SoCs are typically operated from a single power-supply source which is a battery providing a constant supply voltage. In order to reduce power dissipation of the AMS-SoCs, multiple-supply voltage and/or variable-supply voltage is used as an attractive low-power design approach. In the multiple-/variable-supply voltage AMS-SoCs the use of a DC-to-DC voltage-level shifter is critical. The voltage-level shifter is an overhead when its own power dissipation is high. In this article a new DC-to-DC voltage-level shifter is introduced that performs level-up shifting, level-down shifting, and blocking of voltages and is called Universal Level Shifter (ULS). The ULS is a unique component that reduces dynamic power and leakage of the AMS-SoCs while facilitating their reconfigurability. The system-level architectures for three AMS-SoCs, such as Drug Delivery Nano-Electro-Mechanical-System (DDNEMS), Secure Digital Camera (SDC), and Net-centric Multimedia Processor (NMP) are introduced to demonstrate the use the ULS for system-level power management. The article presents a design flow and an algorithm for optimal design of the ULS using a dual-Vth high-κ technique for efficient realization of ULS. A prototype ULS is presented for 32nm nano-CMOS technology node. The robustness of the ULS design is examined by performing three types of analysis, such as parametric, load, and power. It is observed that the ULS produces a stable output for voltages as low as 0.35 V and loads varying from 50 fF to 120 fF. The average power dissipation of the ULS with a 82 fF capacitive load is 5 μ W.