A Scheduler ASIC for a Programmable Packet Switch

Authors:
L. Louis Zhang;Brent Beacham;Massoud Reza Hashemi;Paul Chow;Alberto Leon-Garcia
Affiliations:
-;-;-;-;-
Venue:
IEEE Micro
Year:
2000

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Abstract

We designed a generic, single-queue scheduler engine for use in a programmable packet switch/router to handle IP packets, ATM cells, or a combination of both. Comprising 275,000 gates, the 0.35-micron ASIC is incorporated into a prototype programmable packet switch.