Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
Proceedings of the 19th ACM Great Lakes symposium on VLSI
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Level converters are becoming overhead for the circuits they are being employed in. If their power consumption continues to grow, they will fail to serve the very purpose they were built for. In this paper we propose the application of a dual-T_ox} (DOXCMOS)technique for the power-delay optimization of a DC to DC voltage level converter under oxide thickness T_ox$) and transistorgeometry constraints. The results show power savings of 83 % and delay improvement of 60 % over existing designs. The proposed level converter is capable of performing level-up/down conversion, and blocking of the input signal. The design is area optimal, with a minimum number of transistors. It is a robust design producing a stable output for voltages as low as 0.6 V and loads varying from 10 fF to 200 fF for a 90nm technology. The average power dissipation of the converter with a 45fF capacitive load is 19.89\mu W. The entire design cycle has been carried out up to physical design, including parasitic re-simulation. To the best of the authors' knowledge, this is the first level converter designed using a DOXCMOS technology for power-delay optimization.