Power Aware Design Methodologies
Power Aware Design Methodologies
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs)
ATS '98 Proceedings of the 7th Asian Test Symposium
NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Testing On-Die Process Variation in Nanometer VLSI
IEEE Design & Test
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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In this paper, we present the design of a P4 (Power-Performance-Process-Parasitic) aware voltage controlled oscillator (VCO) at nano-CMOS technologies. Through simulations, we have shown that parasitics and process have a drastic effect on the performance (center frequency) of the VCO. For process variation analysis, we propose a methodology called Design of Experiments-Monte Carlo (DOE-MC), which offers up to 6.25x time savings over a traditional Monte Carlo (TMC) method. A performance optimization of the VCO along with dual-oxide power minimization technique has been carried out in the presence of worst case process. The end product of the proposed methodology is a process aware, performance optimized, dual oxide VCO physical design. We have achieved 25% power (including leakage) minimization with only 1% degradation in center frequency compared to target frequency, in the presence of worst-case process and parasitics. The dual-oxide physical design of the VCO is carried out at 90nm. To the best of the authors' knowledge, this is the first research reporting a dual-oxide nano-CMOS VCO design simultaneously optimized for power (including leakage), performance, parasitics and process.