Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Design of parasitic and process-variation aware nano-CMOS RF circuits: a VCO case study
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A current-starved voltage controlled oscillator (VCO) is treated as a case study and to the best of the authors' knowledge, this is the first VCO design that accounts for both parasitic degradation and process variation together. The physical design of the VCO is carried out in a generic 90 nm Salicide 1.2 V / 2.5 V 1 Poly 9 Metal process design kit. The oscillation frequency is the objective function with the area overhead as constraint. A performance degradation of 43.5 % is observed when the parasitic extracted circuit was subjected to worst case process variation. After a single physical design iteration, the frequency of oscillation was within 4.5 % of the target.