A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO

Authors:
Saraju P. Mohanty;Dhruva Ghai;Elias Kougianos
Affiliations:
-;-;-
Venue:
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Year:
2010

Citing 0
Cited 1

ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management

ACM Journal on Emerging Technologies in Computing Systems (JETC)

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Abstract

We present the design flow for a P4VT (Power-Performance-Process-Parasitic-Voltage-Temperature) aware voltage controlled oscillator (VCO). Through simulations, we have shown that parasitics, process, voltage and temperature have a drastic effect on the performance (center frequency) of the VCO. A design optimization of the VCO, along with dual-threshold power minimization has been performed in the presence of worst-case variations. The end product of the proposed methodology is a P4VT-optimal dual-threshold 90nm VCO layout. We have achieved 16.4% power (including leakage) minimization with 10% degradation in center frequency compared to the target frequency, in the presence of worst-case variations.