Accurate temperature estimation using noisy thermal sensors
Proceedings of the 46th Annual Design Automation Conference
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
A study on global and local optimization techniques for TCAD analysis tasks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design
ISVLSI '12 Proceedings of the 2012 IEEE Computer Society Annual Symposium on VLSI
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We present a novel and efficient thermal sensor design methodology. The growing demand for power management on VLSI systems drives the need for accurate thermal sensors. Conventional design techniques for on-chip thermal sensors in nanometer technologies consume expensive design iterations and result in increased power consumption and area overhead. Power-efficient, high-sensitivity thermal sensors are important for reducing the thermal stress on the systems or circuits which are being monitored. The proposed design flow methodology, which incorporates a stochastic gradient descent (SGD) algorithm, optimizes the power consumption (including leakage) of IC subsystems. An illustration of the proposed design methodology is presented using a ring oscillator (RO) based on-chip thermal sensor which was designed using 45nm CMOS technology. The RO based thermal sensor has a resolution of 0.097^oC/bit. Experimental tests and analysis of the design methodology on a full layout-accurate parasitic netlist of the RO demonstrate the applicability of our methodology towards optimization of the power consumption with temperature resolution as a design constraint. A reduction of power consumption by 52% with a final area of 1389.1@mm^2 is obtained.