Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microelectronic Circuits Revised Edition
Microelectronic Circuits Revised Edition
A Process Variation Tolerant Self-Compensating Sense Amplifier Design
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents research leading to robust nano-CMOS sense amplifier design by incorporating process variation early in the design process. The effects of process variation are analyzed on the performance of a conventional voltage sense amplifier which is used in most DRAMs. A parametric study is performed through circuit simulations to investigate which parameters have the most impact on the performance of the sense amplifier. The Figures of Merit (FoMs) used to characterize the circuit are precharge time, power dissipation, sense delay and sense margin. Statistical analysis is performed to examine the impact of process variations on each FoM. By analyzing the results from the statistical study, a method is presented to select parameter values that minimize the effects of process variation. In this context, the well-established process-level techniques dual-threshold voltage and dual-oxide thickness are, for the first time, investigated for efficient sense amplifier design. Experimental results prove that the proposed approach improves precharge time by 63.3%, sense delay by 53.6%, sense margin by 39.3%, and power dissipation by 23.3% for 45 nm CMOS.