SRAM Local Bit Line Access Failure Analyses
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A new single-ended SRAM cell with write-assist
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Criterion to evaluate input-offset voltage of a latch-type sense amplifier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
The input referred offset voltage occurring in the full latch VDD biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by ±2.5% variation in VT and ±5% variation in β, from typical values. Effect of various design parameters on the sense amplifier offset has been studied and reported. It has been shown that the rise time of the sense amplifier enable signal (SAEN) has a profound effect on the offset voltage. The slower transition of SAEN signal is proposed to result in high speed as well as low-power consumption in SRAM application. An analytical model has been derived for simplified latch to model the effect of rise time of SAEN signal on offset voltage.